FILTER=DISABLED, PAR=EVEN, CHMODE=NORMAL, BRSRCCK=PERIPH_CLK
Mode Register
| FILTER | Receiver Digital Filter 0 (DISABLED): UART does not filter the receive line. 1 (ENABLED): UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). |
| PAR | Parity Type 0 (EVEN): Even Parity 1 (ODD): Odd Parity 2 (SPACE): Space: parity forced to 0 3 (MARK): Mark: parity forced to 1 4 (NO): No parity |
| BRSRCCK | Baud Rate Source Clock 0 (PERIPH_CLK): The baud rate is driven by the peripheral clock 1 (PMC_PCK): The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). |
| CHMODE | Channel Mode 0 (NORMAL): Normal mode 1 (AUTOMATIC): Automatic echo 2 (LOCAL_LOOPBACK): Local loopback 3 (REMOTE_LOOPBACK): Remote loopback |